1. Field of the Invention
The present invention relates to a dual structure Fin Field Effect Transistor (FinFET) having a Fin channel and a method of manufacturing the same, and more particularly, to a FinFET having a dual structure where an N-type FinFET and a P-type FinFET which are formed of solid source material layers are stacked, and a method of manufacturing the same.
The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2006-S006-01, Components/Module technology for Ubiquitous Terminals] in Korea.
2. Discussion of Related Art
As techniques of manufacturing semiconductor devices are developed, attempts are made to decrease the size of the device and increase the operating speed or the like for enhancing performance. Accordingly, Metal Oxide Semiconductor FETs (MOSFETs) as the mainstream of the devices used in electronics today have been also continuously scaled down, and a double gate FinFET and a multi-gate structure are proposed to solve a short channel effect.
FIG. 1 is a perspective view of a conventional FET using a MOSFET. Referring to FIG. 1, a conventional transistor 800 using a MOSFET includes an N-type well 801 and a P-type well 802 formed in a silicon substrate, and a gate insulating layer 810 and gate electrodes 807 and 809 formed on the N-type well 801 and the P-type well 802. A P-type source 803 and a P-type drain 804 are formed in the N-type well 801, and an N-type source 805 and an N-type drain 806 are formed in the P-type well 802. Accordingly, a P-type MOSFET (PMOS) and an N-type MOSFET (NMOS) are formed. When the gate electrodes 807 and 809 are connected in common in the above-described structure, a horizontal type FinFET can be obtained. The NMOS and PMOS of the transistor 800 are insulated by a field oxide layer 808.
However, in the horizontal type transistor 800 having the above-described configuration, the NMOS and PMOS are formed on the same plane, so that the integration density of a circuit is not significantly enhanced when the FinFET is configured even when actual sizes of devices are decreased. Further, in the case of the PMOS, hole mobility is lower than electron mobility so that the width of the PMOS should be formed two to three times larger than the width of the NMOS in order to have the same level of current drivability as the NMOS, and the area of the FinFET actually becomes three to four times larger than the area of the NMOS layout, which thus causes a limit on enhancement of the density of integration.
To solve such a problem, a FinFET having a dual structure is disclosed in Korean Patent Registration No. 10-0583391 entitled “Stack Structured FinFET Transistor and CMOS Inverter Structures and Method for Manufacturing The Same.” However, according to the disclosed invention, ions are required to be selectively implanted into source and drain of each of upper and lower transistors, which cannot be easily accomplished by the current process technology, and the lower device should not be affected by ions to be implanted for forming the source and drain of the upper device. Also, when a contact hole of the lower device is formed, an upper surface should be exposed and a portion of an interlayer dielectric layer should be left on a side surface of the contact hole, which requires a complicated process that cannot be easily implemented.